The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM.
In the semiconductor memory device such as a dynamic RAM or a static RAM, a burn-in is typically performed before or after package process of a chip, in order to the reliability of internal circuits therein. Such a burn-in test is required to detect defects or strength of memory cells stored in the same chip, for which an exterior supply voltage or a higher voltage more than the supply voltage is supplied to each of the memory cells, thereby checking whether the memory cells are in good state or in bad state. The burn-in test has been actually carried out in the semiconductor industry and further much endeavors for performing more effective burn-in test have been made.
In the meanwhile, such a burn-in test is typically different, upon applying a burn-in method to a dynamic RAM and a static RAM, since their memory cell structures are different from each other. As can be well known in the art, in the dynamic RAM, a single memory cell is comprised of one storage capacitor and one access transistor, while in the static RAM, a single memory cell is comprised of six transistors, or two resistors and four transistors. Here, in case of the dynamic RAM, since the memory cell structure is made up of a volatile memory element having a discharging feature of data, the memory cell must restore data at intervals of a constant time, i.e., must execute a refresh operation. But in case of the static RAM, since the memory cell structure is made up of a latch construction, the memory cell does not need to execute the refresh operation separately. Accordingly, it can be appreciated that the burn-in tests are different in the dynamic RAM and the static RAM due to the structural feature of each memory cell. For the details, the following description will be made.
The technique on the burn-in test of the semiconductor memory device particularly having a memory cell structure in the dynamic RAM is disclosed in U.S. Pat. No. 4,380,805 filed Apr. 19, 1983 by the inventor Robert J Proebsting, entitled "Tape Burn-In Circuit". In the prior art, the burn-in test is carried out in a wafer state to reduce the time consumed for the burn-in test. That is, this prior art is defined to the semiconductor memory device such as the dynamic RAM having a memory cell structure necessitating a refresh operation. In operation, there are a plurality of extra pads and a signal is applied thereto to cause all the rows and columns positioned on the same chip to be enabled. Through this process, all of the memory cell in the chip are selected and the burn-in therefor is simultaneously performed in the wafer state. If the burn-in is executed as discussed above, there is an advantage in that the burn-in time spend by the burn-in operation can be considerably reduced, whereas there is a disadvantage in that a separate device capable of performing the burn-in operation in the wafer state has to be used. In addition, a plurality of extra pads as means which supplies a burn-in voltage to the memory cells in the wafer state have to be formed on the same ship.
Meanwhile, the prior art can not been applied to the static RAM since a refresh function used in the dynamic RAM is applied therein. The memory cell in the dynamic RAM is comprised of one storage capacitor and one access transistor, so that no problem occurs even though the burn-in for all the memory cells are carried out at a time. However, since the static RAM does not have any refresh function, the method of accessing the memory cell is achieved only by performing a reading/writing operation. Therefore, in the case where the prior art is applied to the static RAM, the number of memory cells connected to a write driver as a circuit which enables the writing operation to the memory cells of the static RAM becomes large, thus a normal writing operation for each memory cell is not executed and accordingly the burn-in operation for the desired number of memory cells can not be achieved completely. This difficulty has to be considered as the integrity of a chip is increased. Hence, when the burn-in test is performed in the static RAM, the desired number of rows and the desired number of columns have been at the same time enabled typically. If, like the prior an mentioned above, the burn-in test in the wafer state is performed in the static RAM, there are various problems, such as purchase of an expensive equipment required for the burn-in, time restriction consumed for the burn-in, etc. As a result, it has been estimated that the burn-in test of the static RAM in the wafer state suffers from much difficulties.